1. Field of the Invention
The present invention relates to a semiconductor device and, more particularly to a semiconductor device forming a power MOSFET having high cosmic rays radiation hardness.
2. Description of the Related Art
The power MOSFET is widely used as a switching device in a system such as a power supply, a motor driving circuit, or a control circuit. In mounting the power MOSFET on a space rocket or a satellite, it is necessary to prevent the power MOSFET from failure due to entering high-energy heavy ion particles arrived from the space. This necessitates use of a power MOSFET in which a voltage at such failure, i.e. Single Event Burnout, SEB, (hereinafter referred to as SEB voltage) is high.
FIG. 1 is a cross sectional view showing an arrangement of an n-channel power MOSFET traditionally used. In the power MOSFET, on a drain layer 11 of N+ semiconductor substrate, an N− base layer 12 is deposited by epitaxial growth. In a portion on the surface of the N− base layer 12, there is selectively formed a P base region 13. Further, in a portion on the surface of the P base region 13, there is selectively formed an N+ source region 14. In the P base region 13, there is also formed a highly doped P+ base region covering a part of the N+ source region 14. Showing the detail of the highly doped P+ base region, however, is omitted from FIG. 1. In the P base region 13, a surface region between the N+ source region 14 and the N− base layer 12 is made served as a channel region. On the channel region, a gate electrode 16 is formed with a gate insulator film 15 held between the channel region and the gate electrode 16. In addition, there is formed a source electrode 17 in contact with the N+ source region 14 and the P base region 13 in common. On the back of the N+ drain layer 11, there is formed a drain electrode 18.
An on-resistance of the power MOSFET with the arrangement shown in FIG. 1 is given as a sum of a resistance of the channel region, a resistance of the N− base layer 12, and a resistance of the N+ drain layer 11. Of those resistances, the largest one is normally the resistance of the N− base layer 12. For suppressing switching loss as being the smallest possible, the smallest possible on-resistance is preferable. Therefore, the N− base layer 12 is designed to have the least sufficient thickness for keeping a specified breakdown voltage. Namely, in designing a power MOSFET, determination of a breakdown voltage VBR of a device almost determines an impurity concentration ND and the thickness of the N− base layer 12.
The relationship between the breakdown voltage VBR of the device and the impurity concentration ND of the N− base layer 12 is expressed by the following expression (1) with the junction approximated as being a step junction:VBR=(ε·ε0(NA+ND)EBR2)/(2q·NA·ND)  (1) where NA is the acceptor concentration in the P base region 13, ε0 is the permittivity of vacuum, ε is the relative dielectric constant of the semiconductor, q is the charge of electron is q, and EBR is the insulation breakdown electric field strength of the semiconductor (for Si, 3.25×105V/cm).
For NA>>ND, the above expression (1) is approximated by the following expression (2), from which the impurity concentration ND in the N− base layer 12 is determined.VBR=(ε·ε0·EBR2)/(2q·ND)  (2) 
In addition, a width of a depletion layer on the side of the the N− base layer 12 is expressed by the following expression (3) asd=√{square root over (((2ε·ε0·VBR)/(q·ND)))}{square root over (((2ε·ε0·VBR)/(q·ND)))}=2VBR/EBR  (3) 
The actual voltage withstanding design of the device is carried out on the basis of the expression (3) with some margin taken into consideration.
Incidentally, there are various kinds of patent applications about vertical MOSFETs improved for preventing damages of devices due to breakdown (JP-A-59-132671 and JP-A-60-196975).
However, when the power MOSFET with the arrangement as shown in FIG. 1 is applied to space use, there occurs a problem in that high energy heavy ion particles incident on the power MOSFET cause SEB even with an applied voltage of the order of ⅓ to ½ of the breakdown voltage. The SEB can be explained in detail as follows with a mechanism having been clarified by a three-dimensional device simulation.
That is, suppose that, with each of the drain and the gate being negatively biased with respect to the source, respectively, there is incident on the power MOSFET a cosmic ray of high energy heavy ion particles with a range R therein. The incident cosmic ray passes a top end of the N+ source region 14 to reach the N+ drain layer 11, during which the cosmic ray produces electron-hole pairs while losing its energy. A current produced by an incident beam of such cosmic ray sometimes locally exceeds 100,000A per square centimeter.
Produced electrons, being affected by an electric field, flow toward the N+ drain layer 11. While, holes move toward the N+ source region 14, passing through the P base region 13 to be taken out from the source electrode 17. The hole current exceeding a certain value makes the pn-junction between the N+ source region 14 and the P base region 13 forward-biased to cause latch-up, by which electrons are injected from the N+ source region 14. That is, a parasitic npn-transistor is made in being turned on. The injected electrons move along the incident beam path allowing a current to easily flow, and reach the N+ drain layer 11, where the electrons cause dynamic avalanche, by which a large number of electron-hole pairs are produced.
Here, with Jn, Jp, αn, and αp taken as values of an electron current and hole current, impact ionization rates of the electron and hole, respectively, each being a function of the electric field, a carrier pair generation rate G of the semiconductor is expressed by the following expression (4) as,G=αn·Jn+αp·Jp  (4) 
In this case, the values of Jn and Jp are significantly large. Therefore, the value of the carrier pair generation rate G becomes large even in an electric field with an electric field strength far lower than the static insulation breakdown electric field strength (in silicon, 2×105 V/cm). That is, a large number of electron-hole pairs are to be produced. The produced holes flow toward the N+ source region 14 again to enhance latch-up. This causes between the parasitic npn-transistor and the N+ drain layer 11 a positive feedback similar to that in the thyristor mode, by which the current is promptly increased.
Thus, a high-density electron-hole plasma is maintained along the path of the incident beam to finally cause local thermal runaway that results in device breakdown. The time until occurrence of the positive feed back is normally of the order of 1000 picoseconds. In FIG. 2, there are shown examples of respective current waveforms obtained by simulations with and without occurrence of SEB.
In view of the above problem, the invention was made with an object of providing a semiconductor device which forms a power MOSFET provided with sufficient SEB voltage for being applied to space use.